The present invention relates to semiconductor memory devices. More particularly, the invention relates to flash memory devices executing cache read functions.
Driven by ever-growing demands for higher performance contemporary memory systems including flash memory devices have incorporated a cache read functionality. During a cache read operation, previous read data stored in a cache register is output to an external circuit while current read data is read from memory through a main register. An exemplary cache read operation will be described with reference to FIG. 1.
Referring to FIG. 1, a read command, a corresponding read data address, and a read operation start indication are provided to a memory system incorporating flash memory (hereafter, “a flash memory system”) according to a predetermined timing sequence. In the constituent flash memory device, after receiving the read start command, a ready/busy signal R/nB transitions from logically “high” to a logically “low” state (i.e., “goes low”). Operation of the main register is initiated after the ready/busy signal R/nB goes low during a first time period P1. The read data identified by the address is read from memory by operation of the main register during a second time period P2. Then, current read data stored in the main register are transferred to a cache register during a third time period P3. After the current read data is transferred to the cache register from the main register, the ready/busy signal R/nB goes high.
In response to the ready/busy signal R/nB going high, a cache read command is provided to the flash memory device by an external device (e.g., a memory controller in the flash memory system). Upon receiving the cache read command, the ready/busy signal R/nB in the flash memory device goes low during a fourth time period P4 and then returns high. During the fourth time period P4 defined by the transition of the ready/busy signal R/nB, current read data is transferred to the cache register from the main register. Following this read data transfer, the ready/busy signal R/nB goes high. Then, operation of the main register is initiated after the ready/busy signal R/nB goes high beginning a fifth time period P5. Thus, read data is output from memory through the main register and read data stored in the cache register is output to the external device during the fifth and sixth time periods P5 and P6.
According to this sequence of steps in the cache read operation, previous read data is output to the external circuit from the cache register when the main register is initiated during the fifth time period P5. However, noise commonly associated with the provision of power voltages within the flash memory system occur during the output of the previous read data to the external circuit from the cache register. In addition, noise associated with the initiation of main register operation is also apparent during this time frame. Thus, the simultaneous generation of noise by the initialization of main register operation and output of previous read data from the cache register, may generally degrade channel conditions and cause data errors to arise in the read data being transferred.